1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Background Art
Currently, in a flash memory device, a redundant block is used to replace a defective block. However, if the number of defective blocks found in a memory chip is equal to or greater than a predetermined number at shipping inspection, the memory chip is identified as a defective chip.
Japanese Patent Laid-Open No. 1997-146849 discloses a memory reconstruction method for improving the system reliability by isolating a memory in which a fault occurs.
Recently, a flash memory device having a large capacity has been advancing, and in order to meet the needs of further large capacity and reduced area on a planar surface, there has been known a three dimensionally stacked NAND flash memory including a plurality of layers, each of which has a memory cell array, (hereinafter referred to as a memory cell layer) laminated in one chip.